? semiconductor components industries, llc, 2014 july, 2014 ? rev. 10 1 publication order number: mc14001ub/d mc14001ub, mc14011ub ub-suffix series cmos gates the ub series logic gates are constructed with p and n channel enhancement mode devices in a single monolithic structure (complementary mos). their primary use is where low power dissipation and/or high noise immunity is desired. the ub set of cmos gates are inverting non?buffered functions. features ? supply voltage range = 3.0 vdc to 18 vdc ? linear and oscillator applications ? capable of driving two low?power ttl loads or one low?power schottky ttl load over the rated temperature range ? double diode protection on all inputs ? pin?for?pin replacements for corresponding cd4000 series ub suffix devices ? nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? this device is pb?free and is rohs compliant maximum ratings (voltages referenced to v ss ) symbol parameter value unit v dd dc supply voltage range ?0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) ?0.5 to v dd + 0.5 v i in , i out input or output current (dc or transient) per pin 10 ma p d power dissipation, per package (note 1) 500 mw t a ambient temperature range ?55 to +125 c t stg storage temperature range ?65 to +150 c t l lead temperature (8?second soldering) 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. temperature derating: ?d/dw? package: ?7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. see detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. ordering information marking diagram soic?14 d suffix case 751a 1 14 140xxug awlyww http://onsemi.com xx = specific device code a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g = pb?free package
mc14001ub, mc14011ub http://onsemi.com 2 logic diagrams mc14001ub quad 2?input nor gate mc14011ub quad 2?input nand gate v dd = pin 14 v ss = pin 7 for all devices 13 12 9 8 6 5 2 1 3 4 10 11 13 12 9 8 6 5 2 1 3 4 10 11 pin assignments 11 12 13 14 8 9 10 5 4 3 2 1 7 6 out c out d in 1 d in 2 d v dd in 1 c in 2 c out b out a in 2 a in 1 a v ss in 2 b in 1 b 11 12 13 14 8 9 10 5 4 3 2 1 7 6 out c out d in 1 d in 2 d v dd in 1 c in 2 c out b out a in 2 a in 1 a v ss in 2 b in 1 b mc14001ub quad 2?input nor gate mc14011ub quad 2?input nand gate
mc14001ub, mc14011ub http://onsemi.com 3 electrical characteristics (voltages referenced to v ss ) characteristic symbo l v dd vdc ? 55 c 25 c 125 c unit min max min typ (note 2) max min max output voltage ?0? level v in = v dd or 0 v ol 5.0 10 15 ? ? ? 0.05 0.05 0.05 ? ? ? 0 0 0 0.05 0.05 0.05 ? ? ? 0.05 0.05 0.05 vdc v in = 0 or v dd ?1? level v oh 5.0 10 15 4.95 9.95 14.95 ? ? ? 4.95 9.95 14.95 5.0 10 15 ? ? ? 4.95 9.95 14.95 ? ? ? vdc input voltage ?0? level (v o = 4.5 vdc) (v o = 9.0 vdc) (v o = 13.5 vdc) v il 5.0 10 15 ? ? ? 1.0 2.0 2.5 ? ? ? 2.25 4.50 6.75 1.0 2.0 2.5 ? ? ? 1.0 2.0 2.5 vdc (v o = 0.5 vdc) ?1? level (v o = 1.0 vdc) (v o = 1.5 vdc) v ih 5.0 10 15 4.0 8.0 12.5 ? ? ? 4.0 8.0 12.5 2.75 5.50 8.25 ? ? ? 4.0 8.0 12.5 ? ? ? vdc output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) i oh 5.0 5.0 10 15 ?1.0 ?0.25 ?0.62 ?1.8 ? ? ? ? ?0.75 ?0.2 ?0.4 ?1.5 ?1.7 ?0.36 ?0.9 ?3.5 ? ? ? ? ?0.55 ?0.14 ?0.15 ?1.0 ? ? ? ? madc (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) i ol 5.0 10 15 0.64 1.6 4.2 ? ? ? 0.51 1.1 3.4 0.88 2.25 8.8 ? ? ? 0.36 0.7 2.4 ? ? ? madc input current i in 15 ? 0.1 ? 0.00001 0.1 ? 1.0 adc input capacitance (v in = 0) c in ? ? ? ? 5.0 7.5 ? ? pf quiescent current (per package) i dd 5.0 10 15 ? ? ? 0.25 0.5 1.0 ? ? ? 0.0005 0.0010 0.0015 0.25 0.5 1.0 ? ? ? 7.5 15 30 adc total supply current (notes 3, 4) (dynamic plus quiescent, per gate c l = 50 pf) i t 5.0 10 15 i t = (0.3 a/khz) f + i dd /n i t = (0.6 a/khz) f + i dd /n i t = (0.8 a/khz) f + i dd /n adc product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 2. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance. 3. the formulas given are for the typical characteristics only at 25 c. 4. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l ? 50) vfk where: i t is in h (per package), c l in pf, v = (v dd ? v ss ) in volts, f in khz is input frequency, and k = 0.001 x the number of exercised gates per package. ????????????????????????????????? ????????????????????????????????? switching characteristics (note 5) (c l = 50 pf, t a = 25 c) ??????????????? ??????????????? characteristic ????? ????? ???? ???? ???? ???? ???? ???? (note 6) ???? ???? max ??? ??? ??????????????? ??????????????? ??????????????? ??????????????? output rise time t tlh = (3.0 ns/pf) c l + 30 ns t tlh = (1.5 ns/pf) c l + 15 ns t tlh = (1.1 ns/pf) c l + 10 ns ????? ????? ????? ????? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ??? ??? ??????????????? ??????????????? ??????????????? ??????????????? ????? ????? ????? ????? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ??? ??? ??????????????? ??????????????? ??????????????? ??????????????? ????? ????? ????? ????? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ???? ??? ??? ??? ??? c. 6. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance.
mc14001ub, mc14011ub http://onsemi.com 4 ordering information device package shipping ? mc14001ubdg soic?14 (pb?free) 55 units / rail nlv14001ubdg* soic?14 (pb?free) 55 units / rail mc14001ubdr2g soic?14 (pb?free) 2500 / tape & reel NLV14001UBDR2G* soic?14 (pb?free) 2500 / tape & reel mc14011ubdg soic?14 (pb?free) 55 units / rail nlv14011ubdg* soic?14 (pb?free) 55 units / rail mc14011ubdr2g soic?14 (pb?free) 2500 / tape & reel nlv14011ubdr2g* soic?14 (pb?free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable. figure 1. switching time test circuit and waveforms v dd 14 v ss output c l input * 7 pulse generator 20 ns 20 ns input output inverting t phl t plh 90% 50% 10% 90% 50% 10% t thl t tlh v dd 0 v v oh v ol *all unused inputs of and, nand gates must be connected to v dd . all unused inputs of or, nor gates must be connected to v ss .
mc14001ub, mc14011ub http://onsemi.com 5 mc14001ub circuit schematic 14 10 3 v dd 6 5 2 1 v ss 4711 12 13 9 8 mc14011ub circuit schematic (1/4 of device shown) 2, 5, 9, 12 1, 6, 8, 13 7 v ss 14 v dd 3, 4, 10, 11 figure 2. typical voltage and current transfer characteristics figure 3. typical voltage transfer characteristics versus temperature figure 4. typical output source characteristics figure 5. typical output sink characteristics v out , output voltage (vdc) 16 14 12 10 8.0 6.0 4.0 2.0 0 0 2.0 4.0 6.0 8.0 10 12 14 16 8.0 6.0 4.0 2.0 0 i d , drain current (madc) v in , input voltage (vdc) v out , output voltage (vdc) 16 14 12 10 8.0 6.0 4.0 2.0 0 0 2.0 4.0 6.0 8.0 10 12 14 16 v in , input voltage (vdc) i d , drain current (madc) -8.0 -6.0 -4.0 -2.0 0 -10 -10 -8.0 -6.0 -4.0 -2.0 0 v ds , drain voltage (vdc) i d , drain current (madc) 2.0 4.0 6.0 8.0 10 0 0 v ds , drain voltage (vdc) 2.0 4.0 6.0 8.0 10 t a = -55 c t a = +25 c t a = +125 c a b c v gs = -5.0 vdc b c a c b c b a a -10 vdc -15 vdc a b c a b c a b c 5.0 vdc v gs = 10 vdc 15 vdc t a = -55 c t a = +25 c t a = +125 c a b c v dd = 15 vdc t a = +125 c t a = -55 c a b a b t a = +25 c unused input connected to v ss . one input only both inputs 10 vdc 5.0 vdc b a b a b a 15 vdc 10 vdc unused input connected to v ss . v dd = 15 vdc b a a b a b 5.0 vdc 10 vdc
mc14001ub, mc14011ub http://onsemi.com 6 package dimensions soic?14 nb case 751a?03 issue k notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of at maximum material condition. 4. dimensions d and e do not include mold protrusions. 5. maximum mold protrusion 0.15 per side. h 14 8 7 1 m 0.25 b m c h x 45 seating plane a1 a m s a m 0.25 b s c b 13x b a e d e detail a l a3 detail a dim min max min max inches millimeters d 8.55 8.75 0.337 0.344 e 3.80 4.00 0.150 0.157 a 1.35 1.75 0.054 0.068 b 0.35 0.49 0.014 0.019 l 0.40 1.25 0.016 0.049 e 1.27 bsc 0.050 bsc a3 0.19 0.25 0.008 0.010 a1 0.10 0.25 0.004 0.010 m 0 7 0 7 h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.019 6.50 14x 0.58 14x 1.18 1.27 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemni fy and hold scillc and its officers, em ployees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc14001ub/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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